عنوان

Design of phase-locked loop (PLL) for ghost cancellation chip using CMOS technology

Number

TLpq304415004

.Language of Text, Soundtrack etc

انگلیسی

Title Proper

Design of phase-locked loop (PLL) for ghost cancellation chip using CMOS technology

General Material Designation

[Thesis]

First Statement of Responsibility

K. S. Islam

Subsequent Statement of Responsibility

J. S. Linder

Name of Publisher, Distributor, etc.

Texas A&M University - Kingsville

Date of Publication, Distribution, etc.

1997

Specific Material Designation and Extent of Item

95

Dissertation or thesis details and type of degree

M.S.

Body granting the degree

Texas A&M University - Kingsville

Text preceding or following the note

1997

Text of Note

The main objective of this thesis is to design a fully integrated charge pump PLL for application and integration on a high-frequency ghost cancellation chip. Since microprocessor operate at very high clock frequency, it becomes necessary to eliminate the delay between external and internal clocks (clock skew). This thesis will deal with the design of a charge pump phase-locked loop as a part of a high-performance ghost cancellation chip set. A charge-pump phase-locked loop (CPPLL) calibrates the delay per stage of the delay line. Using this technique, it is possible to obtain an accurate phase relationship between an off-chip reference clock and the internal clock signals. This CPPLL will be fully integrated onto a ghost cancellation chip in 2.0-um CMOS technology without the need for external components. (1,2) ftnThis thesis has been partially supported by the NASA grants NAG-5-929 and NAG-9-333.

Applied sciences

Electrical engineering

J. S. Linder

K. S. Islam

Electronic name

p

[Thesis]

276903

a

Y