عنوان

A parallel binary structured LMS algorithm for transversal adaptive filters

شماره

TLpq304115018

زبان متن نوشتاري يا گفتاري و مانند آن

انگلیسی

عنوان اصلي

A parallel binary structured LMS algorithm for transversal adaptive filters

نام عام مواد

[Thesis]

نام نخستين پديدآور

M. Eshghi

نام ساير پديدآوران

J. DeGroat

نام ناشر، پخش کننده و غيره

The Ohio State University

تاریخ نشرو بخش و غیره

1994

نام خاص و کميت اثر

159

جزئيات پايان نامه و نوع درجه آن

Ph.D.

کسي که مدرک را اعطا کرده

The Ohio State University

امتياز متن

1994

متن يادداشت

The adaptation process in digital filters requires extensive calculation. This computation makes adaptation a slow and time consuming process. Simple, but versatile, parallel algorithms for adaptive filters, suitable for VLSI implementation, are in demand. In this dissertation a regular and modular parallel algorithm for an adaptive filter is presented. This parallel structure is based on the Gradient Vector Estimation Algorithm, which minimizes the Mean Square Error. In the parallel method, the tap weights of the adaptive filter are updated every s steps, whereas in the recursive algorithms, the tap weights are updated at each step. For s step update, bit strings of length s are used to derive the terms with which the tap weights of the adaptive filter are calculated. The presented parallel algorithm computes the tap weights at time n + s as a function of the tap weights at time n, the inputs from time n + 1 to n + s 1, and the desired output from time n + 1 to n + s 1. The algorithm can be mapped to a VLSI architecture that is both regular and modular and allows either expansion of the order of the filter or the degree of parallelism obtainable. A comparison between the performance of the parallel LMS algorithm, Fast Exact LMS algorithm, and the parallel binary structured LMS algorithm is presented. Based on the proposed algorithm and employing the maximum pipelining, a VHDL model for an adaptive filter is developed. This model verifies the functional behavior of the algorithm as implemented in hardware. The model also simulates the timing of the circuit. This simulation shows the highly regular and modular structure of the algorithm. It is also a practical evidence that the proposed algorithm is suitable for a VLSI implementaton.

موضوع مستند نشده

Applied sciences

موضوع مستند نشده

Electrical engineering

مستند نام اشخاص تاييد نشده

J. DeGroat

مستند نام اشخاص تاييد نشده

M. Eshghi

نام الکترونيکي

فرمت انتشار

p

نوع ماده

[Thesis]

کد کاربرگه

276903

سطح دسترسي

a

تكميل شده

Y